ancient history about 8...32bit processors (was: patch for DB byte order problem)

[Matthias Andree]

David Relson <relson at osagesoftware.com> writes:

> <rant>
> The 8080 was a tour de force when it first appeared - primitive
> instruction set, not withstanding.  Intel has done an amazing job of
> extending the architecture and maintaining backwards compatibility.

s/backwards compatibility/legacy/ :-)

> Personally, I wish IBM had chosen Motorola for the original PC.  Had
> that happened, we'd all be running machines with reasonable instruction
> sets.  However, IBM didn't do that, and we have all managed to survive -
> somehow.

I was so crazy to buy an 68060 board (with SCSI chip) for my Amiga 4000
some years ago, it cost me a fortune (DEM 1.500 or something at that
time), but I liked hacking away in m68k assembler, and the CPU is
FAAAAAAAAAAAAAAAST at 50 MHz. I'm not using it much, the 15 kHz monitor
died, the A520 died, and the drive (IBM DCAS) is near its exitus (or so
it sounds), no graphics board or flicker fixer or scan doubler, no
ethernet (just 460k8bps serial).

Motorola claims 80 MIPS on average for the 68060 @ 50 MHz, and looking
at how many instructions execute at 1 cycle from cache and can be
scheduled to the sOEP, and a properly predicted branch is pretty cheap
as well, there's not much to ask about that figure. Manually tuned loops
with careful instruction reordering might ramp up close to 100
MIPS. Plus, that CPU needs 1 cycle for FABS/FNEG, 3 cycles for
FMUL/FADD, 37 for FDIV and 68 for FSQRT, assuming data are in FP
registers. Do the P-IV or Athlon XP do a floating point division in 37
cycles? I'm not sure how they stack up.

-- 
Matthias Andree